17.3 TLB Refill Vector Selection
Cause
The Interrupt exception occurs when one of the eight interrupt conditions is asserted. The significance of these interrupts is dependent upon the specific system implementation.
Each of the eight interrupts can be masked by clearing the corresponding bit in the Interrupt-Mask (IM) field of the Status register, and all of the eight interrupts can be masked at once by clearing the IE bit of the Status register.
Processing
The common exception vector is used for this exception, and the Int code in the Cause register is set.
The IP field of the Cause register indicates current interrupt requests. It is possible that more than one of the bits can be simultaneously set (or even no bits may be set) if the interrupt is asserted and then deasserted before this register is read.
On Cold Reset, an R4400 processor can be configured with IP[7] either as a sixth external interrupt, or as an internal interrupt set when the Count register equals the Compare register. There is no such option on the R10000 processor; IP[7] is always an internal interrupt that is set when one of the following occurs:
Software needs to poll each source to determine the cause of the interrupt (which could come from more than one source at a time). For instance, writing a value to the Compare register clears the timer interrupt but it may not clear IP[7] if one of the performance counters is simultaneously overflowing. Performance counter interrupts can be disabled individually without affecting the timer interrupt, but there is no way to disable the timer interrupt without disabling the performance counter interrupt.
Servicing
If the interrupt is caused by one of the two software-generated exceptions (described in Chapter 6, the section titled "Software Interrupts"), the interrupt condition is cleared by setting the corresponding Cause register bit, IP[1:0], to 0. Software interrupts are imprecise. Once the software interrupt is enabled, program execution may continue for several instructions before the exception is taken.
Timer interrupts are cleared by writing to the Compare register. The Performance Counter interrupt is cleared by writing a 0 to bit 31, the overflow bit, of the counter.
Cold Reset and Soft Reset exceptions clear all the outstanding external interrupt requests, IP[2] to IP[6].
If the interrupt is hardware-generated, the interrupt condition is cleared by correcting the condition causing the interrupt pin to be asserted.
Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96
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